FIG. 1 is a simplified flow diagram illustrating a simplified conventional process for designing and fabricating an Application-Specific Integrated Circuit (ASIC) 100 using a standard cell library 101 that is stored in a computer or workstation 110. Standard cell library 101 typically includes several hundred predefined “cells”, which are predefined circuit design components that can be selectively combined using a logic design entry software tool 113 to “capture” a user's circuit design. In one embodiment, the user utilizes an input device (e.g., a mouse and/or keyboard) to select graphical representations of selected cells from library 101, and to link input and output terminals of the selected cells to form a circuit schematic representation of his/her circuit design. Once the logic design is entered, place and route tools 117, also loaded on computer 110, are utilized to generate a place-and-route solution, which arranges the various interrelated cells of the logic design in an efficient two-dimensional spatial relationship that can be fabricated on a chip, and assigns predefined routing tracks that provide signal (interconnect) lines for passing signals between the interrelated cells. A layout tool 119 is then utilized to construct a three-dimensional representation of the actual circuit structures (e.g., regions of doped semiconductor, insulated regions, and metal lines) needed to implement the logic design. Next, this three-dimensional representation is used to generate a set of masks (block 120) that are then used to fabricate ASIC 100 (block 130) using known techniques.
FIG. 2 is a diagram that graphically depicts a portion of standard cell library 101. The various cells stored in standard cell library 101 can be classified in five groups: small-scale integrated (SSI) logic, medium-scale integrated (MSI) logic, datapath circuits, memories, and system-level blocks. SSI logic typically includes simple logic gates, such as AND, NAND, XOR, OR, inverter, buffers, registers and flip-flops. MSI logic typically includes medium-complexity circuits, such as decoders, encoders, adders, parity trees, and comparators. Datapath circuits typically include arithmetic/logic units (ALUs), register files, shifters, bus extractors, and inserters. The memory group includes random-access memory (RAM) circuits, read-only memories (ROMs), and content-addressable memories (CAM) of various sizes. Finally, system-level blocks includes such large-scale circuits as multipliers, microcontrollers, UARTs, and RISC cores. Frequently, SSI logic cells are provided in density-optimized and speed-optimized versions.
As depicted by the graphical representation shown in FIG. 3, each cell in standard cell library 101 includes cell layout information that defines the various structures required to fabricate that cell. For example, a two-input NAND gate cell 300 includes N-type and P-type diffusions regions, polysilicon structures, and metal structures that generate a two-input NAND-type logic gate structure when combined according to known fabrication techniques. The dimensions and relative placement of these various structures are defined in the standard cell library for use during the place, route, and layout generation procedures mentioned above. In particular, the N-type diffusion regions of NAND gate cell 300 are defined by first mask information 301, which is depicted by a first (N) mask 311 that is used when NAND gate cell 300 is included in a user's logic design. Similarly, P-type diffusion regions are depicted by second mask information 303 associated with one or more second (P) masks 313, polysicon gate and connection structures are defined by third mask information 305 associated with a third (POLY) mask 315, and metal connection structures are defined by fourth mask information 307 associated with a fourth (Metal-1 or M1) mask 317. For brevity, FIG. 3 omits additional mask information that is necessary to complete the gate structure, such as information related to via structures needed to provide electrical connections between conductive structures associated with the various depicted masks.
Most cells of a particular standard cell library are typically laid out relative to a routing grid, which defines horizontal and vertical “tracks” where the over-the-cell metal routing is formed. In particular, a standard cell's “height” is determined by the number of horizontal grid lines (“tracks”) extending between the uppermost and lowermost points of the cell, and the cell's “width” is determined by of vertical grid lines (“tracks”) extending between the leftmost and rightmost points of the cell. Typically, to facilitate the placement and routing process, most cells of a standard cell library have the same height (or multiples thereof), and the uppermost and lowermost horizontal tracks of the standard cell are reserved for power (VDD) and ground (VSS), respectively. For example, referring to mask 317 in FIG. 3, NAND gate cell 300 is defined by a height of twelve horizontal tracks (i.e., tracks T0 through T12), with track T0 reserved for carrying ground voltage VSS, and track T12 reserved for carrying system voltage VDD. By defining all other SSI and MSI cells using this twelve-track format, blocks of constant or near-constant height can be formed during placement and layout. Note that the size of each cell is adjusted according to its width: for example, NAND gate cell 300 has a width of five vertical tracks (i.e., tracks V0 through V5), whereas a more complex cell may have a width of ten, twenty, or more vertical tracks. Complex cells, such as memories and system-level blocks, may have “double-height” arrangements where two-sets of twelve tracks are combined in a mirror arrangement (i.e., with the respective VSS tracks formed adjacent to each other).
FIGS. 4(A), 4(B), and 4(C) illustrate a schematic diagram, a placement solution, and a layout solution for a simplified logic design using conventional methods.
Referring to FIG. 4(A), a schematic representation 400-L is entered using an entry tool (e.g., logic design entry tool 113; see FIG. 1) by a user. Schematic representation 400-L includes three NAND gate cells 300-1, 300-2, and 300-3, each NAND gate cell being identical to NAND gate cell 300, which is described above with reference to FIG. 3. Signal lines (nets) are also designated using the entry tool. For example a first net 401 is defined for transmitting an input signal IN1 to NAND gate 300-1, a second input line 403 transmits an input signal IN2 to terminals of NAND gate 300-1 and 300-2, and a third input line 405 transmits an input signal IN3 to the second terminal of NAND gate 300-2. The output terminal of NAND gate 300-1 is connected by a net 407 to a first input terminal of NAND gate 300-3, and the output terminal of NAND gate 300-2 is connected by a net 409 to a second input terminal of NAND gate 300-3. The output terminal of NAND gate 300-3 is connected to a net 411.
FIG. 4(B) is a top view showing an exemplary placement solution 400-S for schematic 400-S (FIG. 4(A)). Note that by defining the cells of standard cell library 101 (FIG. 1) according to a predetermined number of horizontal tracks, placement solution 400-S is greatly simplified and highly space efficient. In particular, because each NAND gate has the same height, and because M1 tracks T12 and T0 are reserved for power (VDD) and ground (VSS), respectively, NAND gate cells 300-1 through 300-3 can be arranged in the highly efficient manner shown in FIG. 4(B). As indicated, the cells may be arranged in horizontal groups that are inverted such that tracks T12 and T0 are adjacent to tracks T12′ and T0′ of adjacent cells. In other instances, as mentioned above, a single complex cell may be formed by combining two horizontal groups in a “double-height” arrangement.
As mentioned above, in most standard cell ASICs, the first metal (M1) layer are typically utilized to complete internal cell connections, and subsequent metal layers (e.g., M2, M3, etc.) are typically utilized to provide the external routing structures used to connect associated cells to form the desired completed ASIC. In many instances, above first metal M1, the even metal layers (M2, M4, etc.) are utilized to provide vertical routing channels that are connected by via structures to the underlying polysilicon and/or M1 structures, and odd metal layers (M3, M5, etc.) are utilized to provide horizontal routing channels. For example, FIG. 4(C) is a perspective view showing a simplified routing solution 400-L, which contact vias indicated by double-headed arrows for convenience. Second metal (M2) lines are indicated by heavy black vertical lines (i.e., perpendicular to horizontal tracks T1-T12), and third metal (M3) lines are indicated by heavy black horizontal lines (i.e., parallel tracks T1-T12). In effect, each “track” represents a potential routing path that is used to connect together NAND cells 300-1, 300-2, and 300-3. According to routing solution 400-L, signal lines 401, 403-1, 405, and 411 are implemented using M2 (vertical) metal lines extending along vertical track V1, and signal lines 403-2, 407, and 409 are implemented using M3 (horizontal) metal lines. Note that signal lines 403-1 and 403-2 form net 403 of FIG. 4(A). In this manner, all of the external cell connections associated with a logic design are implemented using the M2 and M3 metal layers of the associated CMOS fabrication process. Thus, in a given completed ASIC device, all of the cells may be completely covered by horizontal and vertical routing lines. By reserving the metal layers above M1 (e.g., M2, M3, etc.) for external routing connections in a standard cell ASIC, automatic placement and routing of the ASIC is greatly simplified, resulting in very good cell placement densities.
FIG. 5 is a perspective view depicting a mask set 510 superimposed over standard cell ASIC 100, which was introduced in FIG. 1. Mask set 510 represents the final (fabrication) step in which the placement and routing solutions discussed above are used to form mask set 510, which is then used during the fabrication of ASIC 100. Note that standard cell ASIC 100 includes a plurality of cells 502 and surrounding bonding pads 505 that are laid-out in the manner defined during the place-and-route process (described above). Mask set 510 includes a first group 512 of masks that include predefined structures used to form cells 502, pads 505, and other predefined structures of device 100. For example, first group 512 includes the P mask, N mask and POLY mask indicia associated with NAND cell 300 (described above), along with structures associated with all of the other cells, arranged in the manner determined during the placement process. Mask set 510 also includes a second group 514 of masks associated with the metal layers used to complete internal cell connections and external cell routing structures in the manner described above.
A problem associated with the conventional standard cell ASICs described above is that restricting internal cell connections to the first metal (M1) layer necessarily requires a large cell height (i.e., cells that span a large number of horizontal tracks). For example, most current standard cell libraries are similar to cell library 101 in that all SSI and MSI cells have cell heights of ten to twelve tracks or more (using 0.12 um technology). This relatively large cell height produces a larger transistor size and layout size. Therefore, ASICs formed using such conventional standard cell libraries exhibit relatively high power consumption, high loads, greater wire capacitance (due to the larger cell sizes), and larger layout sizes. In addition, this larger cell height results in ASICs that take up most of the standard cell core area, making ASIC chips bigger and bigger, and causing significant power distribution problems.
One approach to addressing the above problem would be to simply design a standard cell library based on a smaller cell height (e.g., less than ten horizontal tracks). However, while the design of many SSI cells based on such smaller cell heights is relatively easy, more complex cells require elaborate and extremely long cell widths to complete all necessary internal connections using M1 lines. That is, by eliminating the number of horizontal routing channels over which internal cell connections can be made by M1 structures, the width of certain complex cells must be “stretched” to accommodate all necessary connections. Accordingly, by decreasing the number of horizontal routing channels without decreasing transistor size, the size of some complex cells can actually increase. Further, when the number of horizontal routing channels is too small, in some instances it simply becomes impossible to make all necessary internal connections using M1 structures.
What is needed is a method for developing a standard cell library such that the cells have a reduced cell height without increasing the size of complex cells.